This Quiz article provides multiple choice questions and answers on digital logic design. This is a required course for many electrical engineers and can be a challenging subject. With this resource, you can test your knowledge and keep up with the latest design trends.
Digital Logic Design Multiple Choice Questions with Answers pdf for MCA, BCA, and other IT Academic and Competitive examinations.
Brief Introduction to Digital logic design
Digital Logic Design is the process of designing and constructing digital circuits. The design can be done in a number of different ways, but all involve calculating voltages and currents and then manipulating these numbers to create a working circuit.
There are many different tools that can be used for this purpose, but the most common ones are schematic software programs and breadboard software.
Digital Logic Design Multiple Choice Questions with Answers
1. ___ circuits are those whose outputs depend only on the current inputs.
Answer: Combinational
2. CPU stands for ___.
Answer: Central Processing Unit
3. Multiplexers are examples of combinational circuits. (State true or false)
Answer: True
4. A ___ adder is a digital circuit that accepts two inputs and performs addition on them and generates two outputs known as sum(S) and carry(C).
Answer: Half
5. A full adder is a digital circuit that can handle carry input. (State true or false)
Answer: True
6. The ___ is a combinational circuit that is used to perform the subtraction of two bits.
Answer: Half subtractor
7. The ___ is used to perform subtraction of three bits, input A (minuend), input B (subtrahend), and third input called ___ and produces two outputs D (difference) and B (borrow).
Answer: Full subtractor, Borrow in
8. The ___ adder that adds two four-bit numbers is called a 4-bit parallel adder.
Answer: Parallel
9. A parallel binary subtractor that subtracts two n bit binary numbers in parallel is called a full binary subtractor. (State true or false)
Answer: False
10. A ripple carries adder is called so because each carry bit gets rippled into the next stage. (State true or false)
Answer: False
11. One of the most serious drawbacks of this adder is that the delay increases linearly with the ___.
Answer: Bit length
12. ___adders do not wait for the carry to ripple through the circuit.
Answer: Carry look ahead
13. The expression (A + C)(AD + AD) + AC + C can be minimized to ___.
Answer: A+C
14. A ___is a visual representation of a Boolean function.
Answer: Karnaugh map (K-map)
15. In a K map, a group of eight 1’s is called ___.
Answer: Octet
16. Don’t care value may be considered as ___ in case of SOP and ___ in case of POS expressions respectively.
Answer: 1, 0
17. The simplified form of the expression using the K-map is ___.
Answer: F= AB+BC
18. A ___ is an implicant of the function that is not included in any other implicant of the function.
Answer: Prime implicant
19. When the number of variables is more than six in a given Boolean expression, Quine–McCluskey (Q-M) method will be used. (State true or false)
Answer: True
20. The implementation of a Boolean function with ___ logic requires that the function be simplified in the sum of product form.
Answer: NAND-NAND
21. The NOR function is a dual of the ___ function.
Answer: NAND
22. In the product of sums form, we implement all sum terms using AND gates. (State true or false)
Answer: False
23. ___ of a number is formed by obtaining 9’s complement of a number and adding 1 to the 9’s complement.
Answer: 10’s
24. A ___ bit is an extra bit attached to a binary message to make the total number of 1’s either odd or even.
Answer: Parity
25. ___ gates are useful for generating and checking a parity bit that is used for detecting/correcting errors during the transmission of binary data over communication channels.
Answer: Exclusive OR
26. A multiplexer with 2n data input lines requires ___ number of “control” or select lines to select the input line.
Answer: n
27. A 4: 1 Mux selects one of the input lines and connects it to the output line using 2 select lines. (State true or false)
Answer: True
28. Demultiplexer is also called ___.
Answer: Data distributor
29. ___ accepts an active level (i.e. HIGH) on one of its inputs and converts it into coded output such as binary or BCD.
Answer: Encoder
30. LED stands for ___.
Answer: Light Emitting Diode
31. Which of the following is the BCD-to-7-segment decoder/driver
(a) IC 7446
(b) IC 7464
(c) IC 77446
(d) IC 6446
Answer: (a) IC 7446
32. A ___is a combinational logic circuit that compares the magnitude of two binary numbers and determines if one number is greater than, less than, or equal to the other number.
Answer: Magnitude comparator
33. IC 7485 which is a ___bit comparator.
Answer: 4
34. BCD adder is a circuit that adds two BCD digits and produces some output digit which is also a BCD. (State true or false)
Answer: True
35. BCD subtractor does the subtraction using either ___ complement method or ___ complement method.
Answer: 9’s, 10’s
36. In case SR latch using NOR gates, the ___condition exists when S=R=1.
Answer: Forbidden
37. In the case of ___flip flop input data appears at the output after some time.
Answer: D
38. When J=K=1 and CLK=1, the flip flop toggles as long as the clock signal is HIGH (True or False?).
Answer: False
39. The race around condition exists in ___ flip flop.
Answer: JK
40. T flip flop state toggles when T=1 and CLK=1. (State true or false)
Answer: True
41. When a flip flop responds to the HIGH or LOW level of the clock signal it is called ___ triggering.
Answer: Level
42. When a flip-flop change states either when the clock pulse is changing from LOW to HIGH or from HIGH to LOW, then it is called ___.
Answer: Edge triggering
43. Master-slave flip flop will avoid the ___ condition.
Answer: Race around
44. Preset and Clear inputs are called ___ inputs.
Answer: Asynchronous
45. A ___ circuit is a circuit whose output depends on both the current inputs and the past inputs.
Answer: Sequential
46. Sequential circuit uses the combinational logic circuit, memory, and clock signal for its operation. (True or False?)
Answer: True
47. In ___ sequential circuit an event does not wait for timing pulses.
Answer: Unclocked
48. Any device or circuit that has two stable states is called ___.
Answer: Bistable
49. The term flip-flop is used exclusively for ___ circuits.
Answer: Clocked
50. The ___ is a digital sequential circuit that counts the number of input pulses applied.
Answer: Counter
51. Register is a group of ___.
Answer: Flip-flops
52. ___ is a group of flip-flops combined and connected together to facilitate the movement of data bits from one flip flop to another.
Answer: Shift Register
53. Shift registers are used only for data storage but not for the movement of data. (State true or false)
Answer: False
54. SIPO stands for___.
Answer: Serial-in to Parallel-out
55. In ___ shift register, the data input is given in parallel to the input line of each of the flip-flops, and outputs are read out serially from the single output line (Serial Data Out).
Answer: Parallel-In, Serial-Out (PISO)
56. In the PIPO shift register a single clock pulse is sufficient to store and read the data bits. (State true or false)
Answer: True
57. A shift register that can shift the data in both directions (shift either left or right) is called a ___ shift register.
Answer: Bi-directional
58. A shift register that can shift the data in both directions as well as load it serially and parallelly is known as a ___ shift register.
Answer: Universal
59. The integrated circuit (IC) chip 74LS194 is a universal shift register (State true or false)
Answer: True
60. A shift register that can exhibit a specified sequence of states like that of a counter is known as ___.
Answer: Shift register counters
61. An n-stage Johnson counter yields a count sequence of length 4n. (True or False?).
Answer: False
62. SISO shift register can be used to introduce a time delay. (True or False?)
Answer: True
63. In the case of universal shift register IC 74LS194, shift-right is done synchronously with the positive edge of the clock when S0 is High and S1 is Low. (State true or false)
Answer: True
64. A ___ is a digital circuit that generates a desired sequence of bits in synchronization with a clock.
Answer: Sequence generator
65. In ___ counters a common clock is connected to clock inputs of all the flip flops.
Answer: Synchronous
66. A 3 bit asynchronous up counter counts from ___ in an upward direction.
Answer: 0 to 7
67. We can build a faster counter by clocking all flip-flops. (True or False?)
Answer: True
68. When the control input count-up/down=0 in the Up/Down counter, then the counter works as an up counter. (State true or false)
Answer: False
69. In many applications, it is important to decode different states of the counter whose number equals the modulus of the counter. (True or False?)
Answer: True
70. The ___ representation of a sequential circuit consists of three sections labeled present state, next state, and output.
Answer: State table
71. An n-bit binary counter consists of n flip-flops and can count in binary from ___.
Answer: 0 to 2n – 1
72. How many flip-flops are required to design a Mod-6 counter?
Answer: Three(3)
73. ___ of a counter is the number of different states that a counter can go through before it comes back to the initial state to repeat the count sequence.
Answer: Modulus
74. When a product of sums form of a logic expression is in canonical form, each sum term is called a ___.
Answer: Maxterm
75. The canonical form of the expression X + XY’ is ___.
Answer: XY + XY′
76. A ___ is an electronic circuit that has one or more inputs but only one output.
Answer: Logic gate
77. Less number of gates means less power consumption. (State true or false)
Answer: True
78. The Boolean expression X+X′Y+Y′+(X+Y′) X′Y after simplification yields ___.
Answer: 1
You may read Logic Design MCQs
Conclusion:
Digital logic design is an important process in the development of digital systems. It is used to create the basic building blocks of these systems, which are then used to create more complex structures.
By understanding the principles behind digital logic design, you can develop a deeper understanding of how digital systems work and be better prepared to work with them.
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