Top 100 Digital Electronics MCQ with answers pdf download for students who are preparing for IT gates examination.
Are you a student gearing up for an upcoming exam in the field of digital electronics? Are you seeking a comprehensive resource that can provide you with ample practice questions and their corresponding answers? Look no further, as this article is here to cater to your needs!
In this digital age, where technology plays a vital role in our lives, mastering the concepts of digital electronics has become increasingly essential. To aid you in your exam preparation, we have compiled a list of the top 100 multiple-choice questions (MCQs) on digital electronics along with their respective answers.
Whether you are looking to brush up on your knowledge or test yourself before the big day, this PDF download will serve as an invaluable tool.
Top 100 Digital Electronics MCQ with answers
1. A digital circuit processes ___ signals.
Ans. Digital
2. A signal which varies continuously concerning time, and can take any value is called ___.
Ans. Analog Signals
3. A ___ signal is a signal that is not continuous in time and amplitude.
Ans. Digital
4. A group of any 8 bits is called ___.
Ans. Byte
5. In TTL input voltage profile, the Vmin= ___ Volts and V max = ___ volts.
Ans. 0, 0.8
6. The time between the rise and the fall of a single pulse is called the___.
Ans. Pulse width(tw)
7. A periodic pulse waveform is one that does not repeat itself at a fixed interval of the period (T). (State true or false)
Ans. False
8. If 0V and 2V are the two voltage levels, then they are represented in the negative logic system as ___.
(a) 0V=High, 2V=Low
(b) 0V= Low, 2V=High
Ans. a) 0V=High, 2V=Low
9. The important logic operations are: ___.
(a) Only AND and NOT
(b) Only AND, and OR.
(c) Only OR, and NOT
(d) AND, OR, and NOT.
Ans. D) AND, OR, and NOT
10. In the case of AND operation, if all the inputs are 1, then the result of AND operation is ___.
Ans. 1
11. ___ logic is not synchronized by a clock signal.
Ans. Asynchronous sequential
12. A ___ is a type of logic circuit whose output depends not only on the present value of its input signals but also on the history of its inputs.
Ans. Sequential logic
13. A transistor acts as a ___ and, can represent the binary number.
Ans. Switch
14. The base of a decimal number system is ___.
Ans. 10
15. The base of the ___ system is 2 because there are only two digits.
Ans. Binary number
16. The base of the Hexadecimal number system is ___.
Ans. 16
17. The decimal equivalent of 144.20753)8 is _____.
Ans. 100.26510
18. The hexadecimal value for (15054.166464)8 is ___.
Ans. 1A2C.3B4D
19. The binary additions of 1 + 1 + 1 = ___.
Ans. (11)2
20. When we subtract 1 from 0, (i.e. 0-1), we require a borrow from the next higher column. (State true or false)
Ans. True
21. In sign-magnitude form, the number (10100)2 represents ___ in decimal.= (─ 4)10
Ans. (─ 4)10
22. 1’s complement of Binary number 101010 is ___.
Ans. 010101
23. The 2’s complement of Binary number 00101 is ___.
Ans. 11011
24. 2’s complement is not used to represent negative numbers. (State true or false)
Ans. False
25. In 1’s complement subtraction, we take the 1’s complement of the minuend. (State true or false)
Ans. False
26. In 1’s complement subtraction, if there is a carry after addition, then the result is ___.
Ans. Positive
27. When we subtract (1101)2 from (1001)2 using 2’s complement method, the result is in ___ form.
Ans. 2’s complement
28. 2’s complement subtraction of 10001- 1001= ___.
Ans. 1000
29. The number system is a collection of the number to represent the quantifiable information. (State true or false)
Ans. True
30. In the decimal number system we have ten different digits 1, 2, 3, 4, 5, 6, 7, 8, 9, and 10. (State true or false)
Ans. False
31. In BCD, each decimal digit is represented by a ___ bit binary code.
Ans. Four
32. In BCD, which of the following codes is invalid?
(a) 1000
(b) 1011
(c) 0101
(d) 1001
Ans. 1011
33. The BCD code for decimal number (6838)10 is ___.
Ans. 0110100000111001(BCD)
34. The BCD code 1001011000010101 represents ___ in decimal.
Ans. 9615
35. ___ systems store the most significant byte of a word in the smallest address and the least significant byte is stored in the largest address.
Ans. Big-endian
36. For decimal number 235, the packed BCD is ___.
Ans. 0000 0010 00000011 00000101
37. The ___ code is an unweighted code.
Ans. Gray
38. The Gary code is called unit distance code because there is a single bit change when we go from one code to the next successive code. (State true or false)
Ans. True
39. The Gray code for binary number110010 is ___.
Ans. 101011
40. The codes that can represent both letters and numbers are called ___ codes.
Ans. Alphanumeric
41. ASCII stands for ___.
Ans. American Standard Code for Information Interchange
42. ___ is also an alphanumeric code used by IBM mainframes for its operating systems.
Ans. EBCDIC
43. The code ___ is the same for the letter N in ASCII and + sign in EBCIDIC code.
Ans. 4E
44. ___ provides a unique number for every character, irrespective of the platform, program, and language.
Ans. Unicode
45. ___ is the detection of errors caused by noise or other impairments during transmission from the transmitter to the receiver.
Ans. Error detection
46. In the case of odd-parity the parity bit is chosen such that the total number of 1s (including the parity bit) is odd. (State true or false)
Ans. True
47. Message 010 with odd parity will be sent as ___.
Ans. 0010
48. When an input or output line on a logic circuit symbol has no bubble on it, that line is said to be ___.
Ans. Active-HIGH
49. The gates which can produce any logic functions are called ___ gates.
Ans. Universal
50. How many NAND gates are required to realize a AND function?
Ans. Two
51. A quantitative measure of Noise immunity is called ___.
Ans. Noise Margin
52. The maximum number of inputs that can be connected to a logic gate without any impairment of its normal operation is referred to as ___.
Ans. Fan-in
53. ___ of a gate is defined as the maximum number of other inputs that can be driven from a single output of a gate without causing any false output.
Ans. Fan-out
54. High-level output voltage (VOH) is the minimum voltage level available for a logical 1 at an input. (State true or false)
Ans. False
55. ___ is a table that lists all possible input combinations and corresponding outputs.
Ans. Truth table
56. ___ produces a high output (i.e. logic 1) when one or more of its inputs are high and it produces a low output (i.e. logic 0) when all the inputs are low.
Ans. OR gate
57. The ‘Exclusive-NOR’ gate is a circuit that will give a high output when an odd number of its inputs are HIGH (i.e. 1), otherwise, it will give a LOW (i.e. 0) output. (State true or false)
Ans. False
58. ___ is the symbol for the AND operation.
Ans. A dot (•)
59. The mathematical expression to represent the logical OR operation is given by___.
Ans. A + B
60. The value of a NOT expression is always opposite to that of the input value. (true or false)
Ans. True
61. In 1854, ___ developed Boolean algebra.
Ans. George Boole
62. Boolean addition (+) is similar to ___ function and Boolean multiplication (•) is similar to ___ function.
Ans. OR, AND
63. A+B = B+A is ___ law of addition.
Ans. Commutative
64. A + A B= ___.
Ans. A + B
65. According to one of the Demorgan’s theorems, the complement of the sum of variables is equal to the product of the complements of the variables. (State true or false)
Ans. True
66. A ___ is an expression formed with binary variables, the two binary operators AND and OR, one unary operator NOT, parentheses, and an equal sign.
Ans. Boolean function
67. Dual of the Boolean expression AIBI + ABI is ___.
Ans. (AI+ BI ) ( A+BI )
68. A ___ expression consists of several product terms logically added.
Ans. Sum of products (SOP)
69. A standard POS expression is also called ___.
Ans. Canonical POS form
70. When a sum of products form of a logic expression is in canonical form, each product term is called ___.
Ans. Minterm
71. A ___ takes digital data at its input and converts it into an analogue voltage or current that is proportional to the weighted sum of digital inputs.
Ans. D/A converter
72. The ___of a D/A converter is the difference between the actual analogue output and the ideal expected output when a given digital input is applied.
Ans. Accuracy
73. ___ is the ratio of the largest output to the smallest output, excluding zero, expressed in dB.
Ans. Dynamic range
74. In weighted resistance, values are weighted following the ___ weights of the digital inputs.
Ans. Binary
75. The advantage of a weighted D/A converter is that resistors used in the network have a wide range of values (True or False?).
Ans. False
76. The process of conversion of the analogue signal to a digital signal is referred to as___.
Ans. analogue-to-digital conversion
77. The resolution of the A/D converter is the number of ___values it can produce over the range of analogue values.
Ans. Discrete
78. Dither is a very small amount of ___ noise which is added to the input before conversion.
Ans. Random
79. The accuracy represents the actual analogue input and the full-scale weighted equivalent of the output code corresponding to the actual analogue input. (True or False?)
Ans. True
80. A successive-approximation ADC uses a ___ to successively narrow a range that contains the input voltage
Ans. Comparator
81. In integrating ADC unknown input voltage is applied to the input of the integrator and allowed to ramp for a fixed period called ___.
Ans. Run-up period
82. Counter Type ADC uses a ___ that feeds a DAC.
Ans. Up-down counter
83. For the counter with three flip-flops, the natural count is equal to ___.
Ans. 8
84. In ___ counters all the flip-flops are not clocked by the same clock and all flip-flops do not change their state in exact synchronism with the applied clock pulses.
Ans. Asynchronous
85. ___ drives are plug-and-play flash-memory data storage devices integrated with the USB interface.
Ans. USB flash
86. PLD stands for ___.
Ans. Programmable logic device
87. In PLDs, the functions are defined at the time of manufacture. (State true or false)
Ans. False
88. PLDs provide an array of ___ gates and ___ gates on a single chip.
Ans. AND, OR
89. SPLD is the acronym for ___
Ans. Simple Programmable Logic Device
90. In ___, the AND array is programmable and the OR arrays are fixed.
Ans. PAL
91. GAL has the same logical properties as that of PAL but can be erased and reprogrammed. (True or False?).
Ans. True
92. A Complex Programmable Logic Device (CPLD) is a combination of a fully programmable AND/OR array and a bank of ___.
Ans. Macrocells
93. The advantage of CPLDs is that more complex designs can be implemented. (State true or false)
Ans. True
94. FPGA stands for ___
Ans. Field Programmable Gate Array
95. The primary memory uses memory cells to store the number and the number stored can be changed over time. (State true or false)
Ans. True
96. ___ memory loses its contents when power is turned off.
Ans. Volatile
97. In a computer system, ROM is used to store data, program instructions, and the results of any intermediate calculations. (State true or false)
Ans. False
98. EPROM stands for ___.
Ans. Erasable Programmable Read-Only Memory
99. The ___ is a graphical representation of different states of a given sequential circuit.
Ans. State diagram
100. The ___ table lists the present state, the next state, and the flip-flop inputs required to achieve that.
Ans. Excitation
Conclusion
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