Computer Organization and Architecture MCQ with Answers pdf

Computer Organization and Architecture MCQ with Answers pdf for the preparation of MCA, BCA, MSC IT, BSC IT academic and competitive exams.

1. The word digital implies that the information on the computer is represented by variables that take a limited number of ___ values.
Ans. discrete

2. The ___ of the computer consists of all the electronic components and electromechanical devices that comprise the physical entity of the device.
Ans. hardware

3. The ___ of a computer consists of a collection of programs whose purpose is to make more effective use of the computer.
Ans. system software

4. The ___ contains electronic circuits for communicating and controlling the transfer of information between the computer and the outside world.
Ans. input-output processor (IOP)

5. ASCII stands for ___.
Ans. American Standard Code for Information Interchange

6. The operations executed on data stored in registers are called ___.
Ans. microoperations

7. The symbolic notation used to describe the microoperation transfers among registers is called a___.
Ans. register transfer language (RTL)

8. The register that holds an address for the memory unit is usually called a ___.
Ans. memory address register (MAR)

9. It is convenient to separate the control variables from the register transfer operation by specifying a___.
Ans. control function

10. A more efficient scheme for transferring information between registers in a multiple-register configuration is a ___.
Ans. common bus system

11. ___ are used for business data processing when computing and storage capacity is larger than what the minicomputers can handle.
Ans. mainframes

12. ___ refers to those attributes of a computer system that are visible to a programmer.
Ans. architecture

13. A ___ is an entity that interacts in some or the other way with its external environment.
Ans. computer

14. Bus can also be a wire or a communication line or in general, it can be referred to as a ___.
Ans. system interconnection

15. ___ performs the calculations on the input data.
Ans. arithmetic logic unit (ALU)

16. CPU consists of a set of registers that function as a level of memory above ___.
Ans. main memory and cache memory

17. ___ enables the machine or assembly language programmer to minimize main memory references by the use of registers.
Ans. user-visible registers

18. Flags of 8085 are nothing but ___.
Ans. conditional codes

19. ___ number of flag bits is defined in 8085.
Ans. five

20. The processing required for a single instruction is called a ___.
Ans. instruction cycle

21. The collection of paths for connecting the modules is called the ___.
Ans. interconnection structure

22. The location of the memory is provided by the input called ___.
Ans. address

23. A bus that carries a word to or from memory is called ___.
Ans. data bus

24. A bus that is used to carry control signals is ___.
Ans. control bus

25. The method of using the same bus for multiple purposes is known as ___.
Ans. time-multiplexing

26. ___ specifies the operation to be performed.
Ans. operation code or opcode

27. Opcodes are represented using ___.
Ans. mnemonics

28. Floating point numbers are ___.
Ans. real numbers

29. ___ is referred to as ASCII in the USA.
Ans. international reference alphabet (IRA)

30. ___ instructions are reserved for the use of the operating system.
Ans. system control

31. In binary arithmetic, we simply reserve ___ bit to determine the sign.
Ans. one

32. The infinite precision ten’s complement of -2 and +5 is ___ and ___.
Ans. 98, 05

33. The finite precision three-digit ten’s complement of -2 and +5 is ___ and ___.
Ans. 998, 005

34. Using finite precision ten’s complement, if both numbers for addition are positive and results negative, then the circuit reports ___.
Ans. overflow

35. ___ is not very common in the hardware of a computer.
Ans. rational numbers and rational arithmetic

36. Using 4-bit fixed-length binary, the addition of 4 and 14 results in ___.
Ans. overflow

37. The two’s complement of -5 is ___.
Ans. (1011)

38. Floating-point numbers are to represent a number ___.
Ans. as mantissa and an exponent

39. IEEE FPS represents numbers with ___.
Ans. a sign bit, the mantissa and the exponent

40. Floating point hardware usually has a special set of ___ and ___ for performing floating-point arithmetic.
Ans. registers, instructions

41. ___ requires its own local memory in the form of registers.
Ans. CPU

42. ___ is often equated with the main memory.
Ans. internal

43. Disk units have ___.
Ans. direct access

44. ___ is the dominant technology for designing large RAMs.
Ans. MOS

45. Static RAM cells use ___ transistors to store a single bit of data.
Ans. 4 to 6

46. ___ memory contains the copy of portions of the main memory.
Ans. cache

47. In ___ design both CPU and main memory are directly connected to the system bus.
Ans. look-aside design

48. Efficiency of the system that uses cache is ___ when all the references are confined to the cache.
Ans. maximum

49. Data are recorded on and later retrieved from the disk via a conducting coil named ___.
Ans. head

50. User application programs reside in the ___.
Ans. userspace

51. External devices can be broadly classified into ___ categories.
Ans. two

52. ___ is a device that allows a computer to exchange data with remote devices.
Ans. modem or NIC

53. The data rate of a mouse is ___.
Ans. 100 bytes/sec

54. In ___ I/O, the I/O module doesn’t interrupt the CPU.
Ans. programmed

55. In ___, devices and memory share an address space.
Ans. memory-mapped I/O

56. In the ISA bus standard, up to ___ of memory can be addressed for DMA.
Ans. 16 megabytes

57. In the ___ mechanism, the CPU is suspended twice.
Ans. single bus detached DMA

58. A ___ is a device, usually peripheral to a computer’s CPU that is programmed to perform a sequence of data transfers on behalf of the CPU.
Ans. DMA controller

59. Channels must be enabled by the ___ for the DMA controller to respond to DMA requests.
Ans. processor

60. Keeping the interrupts disabled for a long time will increase the ___.
Ans. interrupt latency